The invention relates to a method and circuit for providing convenient, multi-mode interfacing between a delta sigma modulator and another device, such as a digital signal processor (DSP) or a digital filter coupled to a DSP.
Ordinarily, only 2 signals are utilized for communication between a delta sigma modulator and a DSP or other processor or a digital filter such as a decimation filter. For example, one of the signals could be an external clock signal generated by the DSP, and the other signal could be a data output signal generated by the delta sigma modulator. The clock signal is required in addition to the data signal because it is necessary to have a clock signal synchronized to the 1-bit serial data signal generated by a delta sigma modulator in order to convert its 1-bit serial data output signal to a more useful multi-bit word of predetermined resolution.
In the closest prior art, the clock signal and data signal are carried by first and second conductors, respectively, which are directly connected between the delta sigma modulator and a DSP (or other processor, such as a microcontroller). This direct connection technique works effectively and economically if the transducer and delta sigma modulator do not need to be electrically isolated from the DSP. However, in many applications the transducer to be measured is electrically xe2x80x9cfloatingxe2x80x9d at a level that may be hundreds or even thousands of volts above or below the ground level of the DSP or other processor. Consequently, for safety reasons and other reasons, it often is necessary for the transducer and the delta sigma modulator to be electrically isolated from the processor (or a digital filter which would be connected in front of the processor to convert the serial 1-bit data output signal produced by the delta sigma modulator to a more useful multi-bit digital word). The electrical isolation often is accomplished by a pair of optical couplers (or other galvanic isolation devices such as isolation transformers, isolation barrier capacitors, or isolating transistor level shift circuits), one optical coupler being used to couple the clock signal of the delta sigma modulator to or from the processor and the other optical coupler being used to couple the 1-bit serial delta sigma output data signal to an input of the processor. However, it is undesirable to be required to use two optical couplers or two other galvanic isolation devices, because optical couplers and other galvanic isolation devices are very expensive.
Thus, there is an unmet need for a convenient, flexible, inexpensive interface between a delta sigma modulator and a processor (such as a DSP or microcontroller) or a digital filter coupled to an input of the processor.
There also is an unmet need for a way of avoiding the need to use two expensive optical couplers or two other galvanic isolation devices to accomplish analog-to-digital conversion of an analog signal produced by a transducer that is referenced to a first ground voltage and providing the digital output as an input to a processor and/or digital filter that is referenced a second ground voltage which may be very different from the first ground voltage.
There also is an unmet need for a circuit and method that provides synchronized digital signals produced by analog-to-digital conversion of a plurality of analog transducer output signals or the like as inputs to a processor.
There also is an unmet need for a circuit and method for providing communication between a processor and a plurality of delta sigma ADCs coupled to perform analog-to-digital conversion of the outputs of a plurality of transducers or the like using a minimum number of conductors coupled between the processor and the delta sigma ADCs.
Accordingly, it is an object of the invention to provide a multi-mode delta sigma modulator circuit including a flexible interface circuit which is capable of a number of selectable operating modes for coupling its clock input signal and its 1-bit serial data output signal to a digital filter or DSP or other processor for any of a variety of user applications.
It is another object of the invention to provide a multi-mode interface circuit which is capable of a number of selectable operating modes for coupling its clock input signal and its 1-bit serial data output signal to a digital filter or DSP or other processor for any of a variety of user applications.
It is another object of the invention to provide a multi-mode interface circuit which is selectively capable of coupling both clock input information and digital output information of a delta sigma modulator through only a single conductor to a digital filter or DSP or other processor.
It is another object of the invention to provide a multi-mode interface circuit which is capable of coupling both clock input information and digital output information of a delta sigma modulator through only a single optical coupler or other galvanic isolation device to a digital filter or a DSP or other processor, wherein the delta sigma modulator has an analog input coupled to an electrically floating transducer or the like.
Briefly described, and in accordance with one embodiment thereof, the invention provides a multi-mode interface circuit (1) for coupling a delta sigma modulator (24) to a processor or a digital filter (37). The interface circuit (1) includes a decoder 20 for decoding a plurality of mode selection inputs to produce a plurality of control signals (30-32,33-1,33-2). An oscillator (21) is enabled by a first control signal (30) from the decoder to produce a first internal clock signal (INTCLK). A first multiplexer (22) selectively switches the first internal clock signal (INTCLK) or an external clock signal (EXTCLK) onto a first conductor (40) to produce a second internal clock signal (40) thereon. A code generator circuit (23) receives the second internal clock signal (40) and a 1-bit data signal (MDAT) produced by the delta sigma modulator (24), and generates a clock input signal (MCLK) applied to a clock input of the delta sigma modulator (24), a third internal clock signal (41), and a fourth internal clock signal (42). The code generator circuit also generates a phase-shift-modulated signal (43) in response to both the second internal clock signal (40) and the 1-bit data signal(MDAT). A second multiplexer (25) selectively switches one of the third (41) and fourth (42) clock signals, and a predetermined signal onto a clock conductor (13) to produce an output clock signal (CLK) thereon. The second multiplexer (25) also selectively switches the external clock signal (EXTCLK) which, if present, is externally applied to the clock conductor (13), from the clock conductor to an input of the first multiplexer (22). A third multiplexer (26) selectively switches the phase-shift-modulated signal (43) or the 1-bit data signal (MDAT) onto a data output conductor (14) to produce a data output signal (DATA) thereon.
In the described embodiment, the code generator circuit produces the clock input signal (MCLK) in response to the second internal clock signal (40). The code generator circuit includes a divider circuit that divides the clock input signal (MCLK) by 2 to produce the third internal clock signal (41) and divides the clock signal (MCLK) by 4 to produce the fourth internal clock signal (42). The code generator circuit also includes a phase-shift-modulator circuit (23B) that phase-shift-modulates the clock input signal (MCLK) according to the 1-bit data signal (MDAT) to produce the phase-shift-modulated signal (43).
The decoder has first (M0) and second (M1) mode selection inputs. The decoder decodes a first state (0,0) of the first and second mode selection inputs to establish a first mode (Mode 0) wherein a first control signal (30) enables the oscillator (21) to produce the first internal clock signal (INTCLK), a second control signal (31) causes the first multiplexer (22) to switch the first internal clock signal (INTCLK) to the first conductor (40) causing the code generator circuit to produce the clock input signal (MCLK) in response to the first internal clock signal (INTCLK), a third control signal (33-1) causes the second multiplexer (25) to switch the third internal clock signal (41) onto the output clock conductor (13) to produce the output clock signal (CLK) equal to the third internal clock signal (41=INTCLK/2), and a fourth control signal (32) causes the third multiplexer (26) to switch the 1-bit data signal (MDAT) onto the data output conductor (14).
The decoder decodes a second state (0,1) of the first and second mode selection inputs to establish a second mode (Mode 1) wherein the first control signal (30) enables the oscillator (21) to produce the first internal clock signal (INTCLK), the second control signal (31) causes the first multiplexer (22) to switch the first internal clock signal (INTCLK) to the first conductor (40) causing the code generator circuit to produce the clock input signal (MCLK) in response to the first internal clock signal (INTCLK), the third control signal (33-1) causes the second multiplexer (25) to switch the fourth internal clock signal (42) onto the output clock conductor (13) to produce the output clock signal (CLK) equal to the fourth internal clock signal (41), and the fourth control signal (32) causes the third multiplexer (26) to switch the 1-bit data signal (MDAT) onto the data output conductor (14).
The decoder decodes a third state (1,0) of the first and second mode selection inputs to establish a third mode (Mode 2) wherein the first control signal (30) enables the oscillator (21) to produce the first internal clock signal (INTCLK), the second control signal (31) causes the first multiplexer (22) to switch the first internal clock signal (INTCLK) to the first conductor (40) causing the code generator circuit to produce the clock input signal (MCLK) in response to the first internal clock signal (INTCLK), a fifth control signal (33-2) causes the second multiplexer (25) to switch the predetermined signal onto the output clock conductor (13) to cause the output clock signal (CLK) to be equal to the predetermined signal, and the fourth control signal (32) causes the third multiplexer (26) to switch the phase-shift-modulated signal (43) onto the data output conductor (14).
The decoder decodes a fourth state (1,1) of the first and second mode selection inputs to establish a fourth mode (Mode 3) wherein the first control signal (30) disables the oscillator (21), wherein the second control signal (31) causes the first multiplexer (22) to switch the external clock signal (EXTCLK) to the first conductor (40) causing the code generator circuit to produce the clock input signal (MCLK) in response to the external clock signal (EXTCLK), the fifth control signal (33-2) causes the second multiplexer (25) to switch the to the output clock conductor (13) to an input of the first multiplexer (22). The fourth control signal (32) causes the third multiplexer (26) to switch the 1-bit data signal (MDAT) onto the data output conductor (14).